The present disclosure relates to a semiconductor device having a buried-channel metal oxide semiconductor (MOS) transistor and its manufacturing method, and also relates to a solid-state imaging device and its manufacturing method. Furthermore, the present disclosure relates to an electronic unit that uses the solid-state imaging device.
An ordinary MOS transistor, in the related art, that is formed in a semiconductor device or solid-state imaging device is a surface channel MOS transistor, in which a region below a gate electrode is an impurity region having a conductivity type opposite to the conductivity type of the source and drain region. In the surface channel MOS transistor, when a voltage is applied to the gate electrode, a channel including an inverted layer is formed on the front surface of the semiconductor substrate and current flows between the source region and drain region.
Many carrier traps are formed in the vicinity of the interface between the semiconductor substrate and an insulating film, due to the presence of non-bonded atoms on the front surface of a semiconductor substrate. With the surface-channel MOS transistor, in which a channel region is formed on the front surface of the semiconductor substrate, therefore, mobility and noise characteristics are deteriorated by the carrier traps present in the vicinity of the interface between the semiconductor substrate and the insulating film.
By contrast, buried-channel MOS transistors have been proposed in recent years, in which the channel region is formed at a distance from the front surface of the semiconductor substrate by forming an impurity region having the same conductivity type as the source and drain region formed below the gate electrode. Japanese Unexamined Patent Application Publication No. 2006-120679 describes a technology that reduces noise in an amplifier transistor by using a buried-channel MOS transistor as the amplifier transistor in a complementary metal oxide semiconductor (CMOS) solid-state imaging device.
With the solid-state imaging device, however, it is recognized that image quality is significantly affected by 1/f noise proportional to the frequency generated by the amplifier transistor. The root mean square of a noise voltage is given by equation (1) below (see “CCD/CMOS imeiji sensa no kiso to oyo” (fundamentals and application of the CCD/CMOS image sensor) published by CQ Publishing Co., Ltd.).
                                          V            _                    n          2                =                                                            q                2                            ⁢                              d                ox                2                            ⁢                              n                Te                                                                    ɛ                ox                2                            ⁢                              W                eff                            ⁢                              L                eff                            ⁢              f                                ⁢          Δ          ⁢                                          ⁢          f                                    (        1        )            
where nTe is the effective trap density per unit area of the channel, dox is the thickness of the gate insulating film, ∈ox is the dielectric constant of the gate insulating film, Weff is the effective gate width, Leff is the effective gate length, q is the amount of electric charge of electrons, and f is the frequency. As seen from equation (1), noise can be reduced by increasing the gate length and gate width. To reduce noise in the CMOS solid-state imaging device, therefore, the gate length and gate width of the amplifier transistor have been increased.
In addition to reducing noise, another important issue to the CMOS solid-state imaging device is to suppress dark current. Today's CMOS solid-state imaging devices use the shallow trench isolation (STI) technology by which elements are isolated so that charge photoelectrically converted by a photodiode does not leak into pixel transistors constituting a pixel. When the CMOS solid-state imaging device uses element isolation by STI, the pixel size can be reduced and dark current can be suppressed.